page 1 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 www.psemi.com product specification ultracmos ? sp4t tuning control switch, 100?3000 mhz pe613050 features ?? open reflective architecture ?? low on-resistance of 1.6 ? ?? low insertion loss ?? 0.25 db @ 900 mhz ?? 0.40 db @ 2200 mhz ?? high power handling ?? 38.6 dbm @ 900 mhz ?? 37.6 dbm @ 2200 mhz ?? wide power supply range (2.3v to 5.5v) ?? high esd tolerance of 2 kv hbm on all pins ?? applications include ?? tunable antennas ?? tunable matching networks ?? bypassing applications ?? rfid readers figure 2. package type 12-lead 2 ? 2 ? 0.5 mm qfn figure 1. functional diagram product description the pe613050 is an sp4t tuning control switch based on peregrine?s ultracmos ? technology. this highly versatile switch supports a wide variety of tuning circuit topologies with emphasis on impedance matching and aperture tuning applications. pe613050 features low on- resistance and insertion loss across key cellular frequency bands from 100 to 3000 mhz. pe613050 offers high rf power handling and ruggedness, while meeting challenging harmonic and linearity requirements enabled by peregrine?s harp? technology. with two-pin low voltage cmos control, all decoding and biasing is integrated on-chip and no external bypassing or filtering components are required. ultracmos tuning devices feature ease of use while delivering superior rf performance. with built-in bias voltage generation and esd protection, tuning control switches provide a monolithically integrated tuning solution for demanding rf applications. doc?62867
page 2 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 ultracmos ? rfic solutions product specification pe613050 table 1. electrical specifications @ 25c, v dd = 2.75v notes: 1. tapered transmission lines on evaluation board pr ovide optimal matching; no additional components on evaluation boar d required to meet specified performance. see figure 5 for evaluation board layout. 2. open reflective architecture for flexible configuration of switch in tuning application. 3. pulsed rf input with 4620 s period, 50 % duty cycle, measured per 3gpp ts 45.005. parameter condition min typ max unit operating frequency 100 3000 mhz r on rf?ant, on state, dc measurement 1.6 ? c off rf?ant, any off state 0.14 pf insertion loss 1 rf?ant 100?698 mhz 0.20 0.30 db rf?ant 698?960 mhz 0.25 0.35 db rf?ant 960?1710 mhz 0.35 0.45 db rf?ant 1710?2170 mhz 0.40 0.50 db rf?ant 2500?2690 mhz 0.50 0.60 db rf?ant 2690?3000 mhz 0.55 0.70 db isolation 2 rf?ant 100?698 mhz 26 28 db rf?ant 698?960 mhz 25 27 db rf?ant 960?1710 mhz 21 23 db harmonics 3 rf?ant (2fo: 698 to 915 mhz; +35 dbm @ tx) ?62 ?36 dbm rf?ant (3fo: 698 to 915 mhz; +35 dbm @ tx) ?55 ?36 dbm rf?ant (2fo: 1710 to 1910 mhz; +33 dbm @ tx) ?58 ?36 dbm rf?ant (3fo: 1710 to 1910 mhz; +33 dbm @ tx) ?55 ?36 dbm rf?ant (2fo: 698 to 798 mhz; +26 dbm @ tx) ?80 ?36 dbm rf?ant (3fo: 698 to 798 mhz; +26 dbm @ tx) ?82 ?36 dbm rf?ant (2fo: 2500 to 2570 mhz; +26 dbm @ tx) ?70 ?36 dbm rf?ant (3fo: 2500 to 2570 mhz; +26 dbm @ tx) ?70 ?36 dbm imd3 bands i,ii,v,viii, +20 dbm cw @ tx freq, ?15 dbm cw @ 2tx?rx freq, 50 ? , sw on ?120 ?105 dbm switching time 50% vctrl to 90% rf on or 10% rf off 2 5 s start-up time 3 time from v dd within specification to all performanc es within specification 70 s rf?ant 2170?2500 mhz 0.45 0.55 db rf?ant 1710?2170 mhz 19 21 db rf?ant 2170?2500 mhz 18 20 db rf?ant 2690?3000 mhz 15 17 db rf?ant 2500?2690 mhz 17 19 db input ip3 100?3000 mhz 72 dbm
page 3 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 www.psemi.com product specification pe613050 moisture sensitivity level the moisture sensitivity level rating for the pe613050 in the 12-lead 2 ? 2 mm qfn package is msl1. figure 3. pin configuration (top view) table 2. pin descriptions pin no. pin name description 1 v dd supply 2 dgnd digital ground 3 v2 switch control input, cmos logic level 4 v1 switch control input, cmos logic level 5 rf4 rf i/o 6 gnd ground 1 7 rf3 rf i/o 8 ant rf common - antenna 9 rf1 rf i/o 10 gnd ground 1 11 rf2 rf i/o 12 dgnd digital ground 1 13 pad exposed paddle 2 table 5. absolute maximum ratings table 4. operating ranges parameter min typ max unit v dd supply voltage 2.30 2.75 5.50 v i dd power supply current (v dd = 2.75v, +25 c) 140 200 a v ih control voltage high 1.2 1.5 3.1 v v il control voltage low 0 0 0.5 v control input current 1 10 a peak operating rf voltage 1,2 100 mhz?1 ghz 1 ghz?3 ghz 27 3 24 4 vpk vpk t op operating temperature range ?40 +25 +85 c symbol parameter/conditions max unit v esd,hbm hbm esd voltage, all pins* 2000 v t st storage temperature range +150 c v ctrl digital input voltage (v1, v2) 3.6 v v dd supply voltage 5.5 v min ?0.3 ?0.3 ?65 electrostatic discharge (esd) precautions when handling this ultracmos device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the specified rating. latch-up avoidance unlike conventional cmos devices, ultracmos devices are immune to latch-up. notes: 1. between all rf ports, and from rf ports to gnd. 2. pulsed rf input duty cycle of 50% and 4620 s, measured per 3gpp ts 45.005. 3. rf input power of 38.6 dbm, 50 ? . 4. rf input power of 37.6 dbm, 50 ? . exceeding absolute maximum ratings may cause permanent damage. operating should be restricted to the limits in the operating ranges table. operation between operating range maximum and absolute maximum for extended periods may reduce reliability. note: * human body model (mil_std 883 method 3015.7). path v2 v1 rf1?ant 0 0 rf2?ant 1 0 rf3?ant 0 1 rf4?ant 1 1 table 3. truth table notes: 1. all ground pins must be tied together (pins 6, 10, 12). 2. recommend grounding but can be left floating.
page 4 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 ultracmos ? rfic solutions product specification pe613050 figure 4. equivalent circuit model schematic equivalent circuit model description the equivalent circuit model shown in figure 4 can be used to accurately model the impedance, insertion loss, and isolation of the sp4t tuning switch. it provides a very close correlation to measured data and can easily be used in circuit simulation programs. table 7 provides the mapping between the desired switch rf state (rf1 thru rf4) and the state variables (sw1 thru sw4). the equivalent circuit model parameter values can be calculated using equations shown in table 6 . table 6. equivalent circuit model parameters variable equation (sw=0 for off and sw=1 for on) unit c p 0.25 pf c off 0.14 pf r sw1 if sw 1 == 1then 1.6 else 400e3 ? l s 0.4 nh r sw2 if sw 2 == 1then 1.6 else 400e3 ? r sw3 if sw 3 == 1then 1.6 else 400e3 ? r sw4 if sw 4 == 1then 1.6 else 400e3 ? table 7. equivalent circuit model variables rf state variable path v2 v1 sw1 sw2 sw3 sw4 rf1?ant 0 0 1 0 0 0 rf2?ant 1 0 0 1 0 0 rf3?ant 0 1 0 0 1 0 rf4?ant 1 1 0 0 0 1
page 5 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 www.psemi.com product specification pe613050 evaluation board the sp4t switch evaluation board was designed to ease customer evaluation of peregrine?s pe613050. the rf common port is connected through a 50 ? transmission line via the top sma connector, j1. rf1, rf2, rf3 and rf4 are connected through 50 ? transmission lines via sma connectors j3, j5, j2 and j4, respectively. a through 50 ? transmission is available via sma connectors j6 and j7. this transmission line can be used to estimate the loss of the pcb over the environmental conditions being evaluated. the board consists of a 4 layer stack with 2 outer layers made of rogers 4350b ( r = 3.48) and 2 inner layers of fr4 ( r = 4.80). the total thickness of this board is 62 mils (1.57 mm). the inner layers provide a ground plane for the transmission lines. each transmission line is designed using a coplanar waveguide with ground plane (cpwg) model using a trace width of 32 mils (0.813 mm), gap of 15 mils (0.381 mm), and a metal thickness of 1.4 mils (0.051 mm). figure 5. evaluation board layout prt-28405
page 6 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 ultracmos ? rfic solutions product specification pe613050 figure 6. evaluation board schematic through line c3 dni 1 1 3 3 5 5 7 7 2 2 4 4 6 6 8 8 10 10 12 12 14 14 13 13 9 9 11 11 j8 header 14 1 2 j6 smasm 1 2 j1 smasm 1 2 j4 smasm 1 2 j5 smasm c4 dni c2 dni 1 2 j3 smasm 1 2 j7 smasm 1 2 j2 smasm c1 dni 6 rfgnd 1 vdd 4 v1 11 rf2 7 rf3 5 rf4 10 rfgnd 13 paddle 9 rf1 3 v2 2 dgnd 12 test 8 ant u2 pe613050 -qfn_12l_2x2 c5 dni r2 dni r1 dni r3 dni rf1 v2 rf2 vdd rf4 rf3 ant test v1_dut doc-32627
page 7 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 www.psemi.com product specification pe613050 2.00 2.00 a 0.10 c c 0.10 c top view side view bottom view 0.05 c seating plane pin #1 identifier b (x2) 0.10 c a b 0.05 c all features recommended land pattern 0.10 c (x2) 0.800.05 0.800.05 0.200.05 (x12) 1.00 1 3 4 6 7 9 10 12 2.40 0.475 (x12) 0.25 (x12) 0.50 0.85 2.40 0.85 0.152 ref. 0.05 max 0.500.05 0.290.05 (x12) 0.50 (x8) (x8) chamfer 0.25x45 figure 7. package drawing 12-lead 2 ? 2 ? 0.50 mm figure 8. top marking specifications marking spec symbol package marking definition pp ds part number code for pe613050 zz 00?zz last two characters of lot code y 0?9 last digit of year, starting from 2009 (0 for 2010, 1 for 2011, etc.) ww 01?53 work week doc-50486 notes: 1. dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m, 1994. note: (pp), the package marking specific to the pe613050, is shown in the figure instead of the standard peregrine package marking symbol (p). ppzz yww doc-51207
page 8 of 8 ?2013?2014 peregrine semiconductor corp. all rights reserved. doc-32614-4 ultracmos ? rfic solutions product specification pe613050 advance information : the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification: the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification: the datasheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify custom ers of the intended changes by issuing a cnf (customer notification form). the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, utsi and ultracmos are registered trademarks and harp, multiswitch and dune are trademarks of peregrine semiconductor corp. peregr ine products are protected under one or more of the following u.s. patents: http://patents.psemi.com . sales and contact information for sales and contact information please visit www.psemi.com . table 8. ordering information order code package description shipping method PE613050A-Z 12-lead qfn 2 ? 2 ? 0.50 mm package part in tape and reel 3,000 units / t&r ek613050-01 evaluation kit ev aluation kit 1 set / box figure 9. tape and reel specifications tape feed direction
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